A rotated array clustered extended hypercube processor: The RACE-H™ processor

Published

Book Section

© 2008 by Taylor and Francis Group, LLC. Many products require efficient high-performance processing to meet the growing computational requirements of numerous media applications. Tailoring a processor’s architecture and system interfaces to minimize processing overhead and inefficiencies in data transfers is required to provide efficient processing for these media applications. In addition, efficiency and low power require the use of techniques that remove the dependency on the processor clock speed to obtain adequate performance. Applications such as high-definition (HD) multistandard video processing require almost continuous processing at the highest performance level. Because power use is highly dependent on frequency, very little power savings can be achieved in these high-compute applications by varying clock frequencies to minimize power use during less-demanding program segments. Use of a flexible parallel architecture is an important means to provide high performance without having a high dependence on the clock rate.

Duke Authors

Cited Authors

  • Pechanek, GG; Stojancic, M; Barry, F; Pitsianis, N

Published Date

  • January 1, 2007

Book Title

  • Unique Chips and Systems

Start / End Page

  • 107 - 124

International Standard Book Number 13 (ISBN-13)

  • 9781420051742

Citation Source

  • Scopus