Performance of a fast analog VLSI implementation of the DFT
© 1992 IEEE. A fast, analog implementation of the DFT/IDFT requires solutions to the problems of I/O bottleneck encountered by large, parallel input sequences, the slow execution time of long sequential sequences, and the resultant error. We present an architecture based on several modifications to Goertzel's Algorithm that provides balances between input serialization, circuit area, execution time, and output error.
Buchanan, B; Madisetti, V; Brooke, M
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International Standard Book Number 10 (ISBN-10)
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