Performance of a fast analog VLSI implementation of the DFT


Conference Paper

© 1992 IEEE. A fast, analog implementation of the DFT/IDFT requires solutions to the problems of I/O bottleneck encountered by large, parallel input sequences, the slow execution time of long sequential sequences, and the resultant error. We present an architecture based on several modifications to Goertzel's Algorithm that provides balances between input serialization, circuit area, execution time, and output error.

Full Text

Duke Authors

Cited Authors

  • Buchanan, B; Madisetti, V; Brooke, M

Published Date

  • January 1, 1992

Published In

Volume / Issue

  • 1992-August /

Start / End Page

  • 1353 - 1356

International Standard Serial Number (ISSN)

  • 1548-3746

International Standard Book Number 10 (ISBN-10)

  • 0780305108

Digital Object Identifier (DOI)

  • 10.1109/MWSCAS.1992.271089

Citation Source

  • Scopus