Performance of a fast analog VLSI implementation of the DFT
Publication
, Conference
Buchanan, B; Madisetti, V; Brooke, M
Published in: Midwest Symposium on Circuits and Systems
January 1, 1992
A fast, analog implementation of the DFT/IDFT requires solutions to the problems of I/O bottleneck encountered by large, parallel input sequences, the slow execution time of long sequential sequences, and the resultant error. We present an architecture based on several modifications to Goertzel's Algorithm that provides balances between input serialization, circuit area, execution time, and output error.
Duke Scholars
Published In
Midwest Symposium on Circuits and Systems
DOI
ISSN
1548-3746
ISBN
0780305108
Publication Date
January 1, 1992
Volume
1992-August
Start / End Page
1353 / 1356
Citation
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Chicago
ICMJE
MLA
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Buchanan, B., Madisetti, V., & Brooke, M. (1992). Performance of a fast analog VLSI implementation of the DFT. In Midwest Symposium on Circuits and Systems (Vol. 1992-August, pp. 1353–1356). https://doi.org/10.1109/MWSCAS.1992.271089
Buchanan, B., V. Madisetti, and M. Brooke. “Performance of a fast analog VLSI implementation of the DFT.” In Midwest Symposium on Circuits and Systems, 1992-August:1353–56, 1992. https://doi.org/10.1109/MWSCAS.1992.271089.
Buchanan B, Madisetti V, Brooke M. Performance of a fast analog VLSI implementation of the DFT. In: Midwest Symposium on Circuits and Systems. 1992. p. 1353–6.
Buchanan, B., et al. “Performance of a fast analog VLSI implementation of the DFT.” Midwest Symposium on Circuits and Systems, vol. 1992-August, 1992, pp. 1353–56. Scopus, doi:10.1109/MWSCAS.1992.271089.
Buchanan B, Madisetti V, Brooke M. Performance of a fast analog VLSI implementation of the DFT. Midwest Symposium on Circuits and Systems. 1992. p. 1353–1356.
Published In
Midwest Symposium on Circuits and Systems
DOI
ISSN
1548-3746
ISBN
0780305108
Publication Date
January 1, 1992
Volume
1992-August
Start / End Page
1353 / 1356