GreenFlag: Protecting 3D-Racetrack Memory from Shift Errors

Published

Conference Paper

© 2019 IEEE. Racetrack memory is an exciting emerging memory technology with the potential to offer far greater capacity and performance than other non-volatile memories. Racetrack memory has an unusual error model, though, which precludes the use of the typical error coding techniques used by architects. In this paper, we introduce GreenFlag, a coding scheme that combines a new construction for Varshamov-Tenegolts codes with specially crafted delimiter bits that are placed between each codeword. GreenFlag is the first coding scheme that is compatible with 3D racetrack, which has the benefit of very high density but the limitation of a single read/write port per track. Based on our implementation of encoding/decoding hardware, we analyze the trade-offs between latency, code length, and code rate; we then use this analysis to evaluate the viability of racetrack at each level of the memory hierarchy.

Full Text

Duke Authors

Cited Authors

  • Mappouras, G; Vahid, A; Calderbank, R; Sorin, DJ

Published Date

  • June 1, 2019

Published In

  • Proceedings 49th Annual Ieee/Ifip International Conference on Dependable Systems and Networks, Dsn 2019

Start / End Page

  • 1 - 12

International Standard Book Number 13 (ISBN-13)

  • 9781728100562

Digital Object Identifier (DOI)

  • 10.1109/DSN.2019.00016

Citation Source

  • Scopus