Modeling interconnect variability using efficient parametric model order reduction

Conference Paper

Assessing IC manufacturing process fluctuations and their impacts on IC interconnect performance has become unavoidable for modern DSM designs. However, the construction of parametric interconnect models is often hampered by the rapid increase in computational cost and model complexity. In this paper we present an efficient yet accurate parametric model order reduction algorithm for addressing the variability of IC interconnect performance. The efficiency of the approach lies in a novel combination of low-rank matrix approximation and multi-parameter moment matching. The complexity of the proposed parametric model order reduction is as low as that of a standard Krylov subspace method when applied to a nominal system. Under the projection-based framework, our algorithm also preserves the passivity of the resulting parametric models.

Full Text

Duke Authors

Cited Authors

  • Li, P; Liu, F; Li, X; Pileggi, LT; Nassif, SR

Published Date

  • December 1, 2005

Published In

Volume / Issue

  • II /

Start / End Page

  • 958 - 963

International Standard Serial Number (ISSN)

  • 1530-1591

International Standard Book Number 10 (ISBN-10)

  • 0769522882

International Standard Book Number 13 (ISBN-13)

  • 9780769522883

Digital Object Identifier (DOI)

  • 10.1109/DATE.2005.213

Citation Source

  • Scopus