Efficient design-specific worst-case corner extraction for integrated circuits

Conference Paper

While statistical analysis has been considered as an important tool for nanoscale integrated circuit design, many IC designers would like to know the design-specific worst-case corners for circuit debugging and failure diagnosis. In this paper, we propose a novel algorithm to efficiently extract the worst-case corners for nanoscale ICs. Our proposed approach mathematically formulates a quadratically constrained quadratic programming (QCQP) problem for corner extraction. Next, it applies the Lagrange duality theory to convert the non-convex QCQP problem to a convex semi-definite programming (SDP) problem that is easier to solve. Our circuit example designed in a commercial CMOS process demonstrates that the proposed SDP formulation can find the worst-case corners both efficiently and robustly, while the traditional QCQP fails to achieve global convergence. Copyright 2009 ACM.

Duke Authors

Cited Authors

  • Hong, Z; Chen, TH; Ting, MY; Li, X

Published Date

  • November 10, 2009

Published In

Start / End Page

  • 386 - 389

International Standard Serial Number (ISSN)

  • 0738-100X

International Standard Book Number 13 (ISBN-13)

  • 9781605584973

Citation Source

  • Scopus