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Defining statistical timing sensitivity for logic circuits with large-scale process and environmental variations

Publication ,  Conference
Li, X; Le, J; Celik, M; Pileggi, LT
Published in: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
June 1, 2008

The large-scale process and environmental variations for today's nanoscale ICs require statistical approaches for timing analysis and optimization. In this paper, we demonstrate why the traditional concept of slack and critical path becomes ineffective under large-scale variations and propose a novel sensitivity framework to assess the "criticality" of every path, arc, and node in a statistical timing graph. We theoretically prove that the path sensitivity is exactly equal to the probability that a path is critical and that the arc (or node) sensitivity is exactly equal to the probability that an arc (or a node) sits on the critical path. An efficient algorithm with incremental analysis capability is developed for fast sensitivity computation that has linear runtime complexity in circuit size. The efficacy of the proposed sensitivity analysis is demonstrated on both standard benchmark circuits and large industrial examples. © 2008 IEEE.

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Published In

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

DOI

ISSN

0278-0070

Publication Date

June 1, 2008

Volume

27

Issue

6

Start / End Page

1041 / 1054

Related Subject Headings

  • Computer Hardware & Architecture
  • 4607 Graphics, augmented reality and games
  • 4009 Electronics, sensors and digital hardware
  • 1006 Computer Hardware
  • 0906 Electrical and Electronic Engineering
 

Citation

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Li, X., Le, J., Celik, M., & Pileggi, L. T. (2008). Defining statistical timing sensitivity for logic circuits with large-scale process and environmental variations. In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (Vol. 27, pp. 1041–1054). https://doi.org/10.1109/TCAD.2008.923241
Li, X., J. Le, M. Celik, and L. T. Pileggi. “Defining statistical timing sensitivity for logic circuits with large-scale process and environmental variations.” In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 27:1041–54, 2008. https://doi.org/10.1109/TCAD.2008.923241.
Li X, Le J, Celik M, Pileggi LT. Defining statistical timing sensitivity for logic circuits with large-scale process and environmental variations. In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2008. p. 1041–54.
Li, X., et al. “Defining statistical timing sensitivity for logic circuits with large-scale process and environmental variations.” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 27, no. 6, 2008, pp. 1041–54. Scopus, doi:10.1109/TCAD.2008.923241.
Li X, Le J, Celik M, Pileggi LT. Defining statistical timing sensitivity for logic circuits with large-scale process and environmental variations. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2008. p. 1041–1054.

Published In

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

DOI

ISSN

0278-0070

Publication Date

June 1, 2008

Volume

27

Issue

6

Start / End Page

1041 / 1054

Related Subject Headings

  • Computer Hardware & Architecture
  • 4607 Graphics, augmented reality and games
  • 4009 Electronics, sensors and digital hardware
  • 1006 Computer Hardware
  • 0906 Electrical and Electronic Engineering