Multi-Watt, 1-GHz CMOS Circulator Based on Switched-Capacitor Clock Boosting

Journal Article (Journal Article)

There has been significant recent progress in the implementation of integrated non-reciprocal components based on linear periodically time-varying (LPTV) circuits. Nevertheless, integrated circulators still require a leap forward in power handling, clock power consumption, and insertion loss (IL) to become compelling compared with ferrite circulators or integrated reciprocal alternatives, such as the electrical-balance duplexer (EBD). This article introduces three innovations: 1) a new switched-capacitor clock-boosting scheme; 2) high-Bragg-frequency quasi-distributed transmission lines based on periodically loaded inductors; and 3) a new gyrator based on switched partially reflecting t-lines - which enable significant performance improvement for integrated circulators and for LPTV circuits more broadly. These are showcased in a 1-GHz 180-nm SOI CMOS circulator that exhibits 2.1-/2.6-dB TX-ANT/ANT-RX IL (0.3 dB better than prior art), +34-dBm TX-ANT P1 dB (2.5 × or 4 dB better), and 40% lower chip area, all at 39-mW power consumption (4.4 × lower).

Full Text

Duke Authors

Cited Authors

  • Nagulu, A; Chen, T; Zussman, G; Krishnaswamy, H

Published Date

  • December 1, 2020

Published In

Volume / Issue

  • 55 / 12

Start / End Page

  • 3308 - 3321

Electronic International Standard Serial Number (EISSN)

  • 1558-173X

International Standard Serial Number (ISSN)

  • 0018-9200

Digital Object Identifier (DOI)

  • 10.1109/JSSC.2020.3022813

Citation Source

  • Scopus