High-speed clock tree simulation with fast wavelet collocation method
In this paper, we propose a fast wavelet collocation algorithm for high-speed clock tree simulation. Taking advantage of the specific structure of clock trees and the superior computational property of wavelets, the proposed algorithm presents the following merits; (1) It can perform both transient simulation and steady-state analysis with arbitrary input; (2) It employs nonlinear buffer model and nonuniform interconnect wire model; (3) It has a low computational complexity O(N) and can deal with considerably large circuits; (4) The Fast Wavelet Collocation Method works in time domain so that the simulation error in time domain can be well-controlled. Numerical experimental results demonstrate the promising features of the proposed algorithm in high-speed clock tree simulations.
Li, X; Zeng, X; Shi, J; Chen, W; Zhou, D; Ling, X
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