Total Store Order and the x86 Memory Model

Book Section

A widely implemented memory consistency model is total store order (TSO). TSO is used in SPARC implementations and, more importantly, appears to match the memory consistency model of the widely used x86 architecture. This chapter presents this important consistency model using a pattern similar to that in the previous chapter on sequential consistency. We first motivate TSO/x86 (Section 4.1) in part by pointing out limitations of SC. We then present TSO/x86 at an intuitive level (Section 4.2) before describing it more formally (Section 4.3), explaining how systems implement TSO/x86 (Section 4.4), and discussing how systems with TSO/x86 implement atomic instructions and instructions used to enforce ordering between instructions (Section 4.5). We conclude by discussing other resources for learning more about TSO/x86 (Section 4.6) and comparing TSO/x86 and SC (Section 4.7).

Full Text

Duke Authors

Cited Authors

  • Sorin, DJ; Hill, MD; Wood, DA

Published Date

  • January 1, 2009

Book Title

  • Synthesis Lectures on Computer Architecture

Start / End Page

  • 37 - 50

Digital Object Identifier (DOI)

  • 10.1007/978-3-031-01733-9_4

Citation Source

  • Scopus