A Parasitics Extraction and Network Reduction Algorithm for Analog VLSI


Journal Article

This paper discusses an algorithm for the extraction of circuit parasitics in integrated circuits using classical transmission line models. This gives a better account of the dc and ac characteristics of interconnects than models incorporating exclusively either the R or C components. We also detail a network reduction technique used to simplify the extracted RC network at user specified accuracies to manageable complexities, especially for large VLSI circuits. The model and circuit reduction algorithms are applied to practical sample circuits. Results of simulations illustrating the reduction in circuit complexity and the degree of modeling accuracy by these methods are also given. © 1991 IEEE

Full Text

Duke Authors

Cited Authors

  • Pong, TS; Brooke, MA

Published Date

  • January 1, 1991

Published In

Volume / Issue

  • 10 / 2

Start / End Page

  • 145 - 149

Electronic International Standard Serial Number (EISSN)

  • 1937-4151

International Standard Serial Number (ISSN)

  • 0278-0070

Digital Object Identifier (DOI)

  • 10.1109/43.68401

Citation Source

  • Scopus