A Parasitics Extraction and Network Reduction Algorithm for Analog VLSI
Publication
, Journal Article
Pong, TS; Brooke, MA
Published in: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
January 1, 1991
This paper discusses an algorithm for the extraction of circuit parasitics in integrated circuits using classical transmission line models. This gives a better account of the dc and ac characteristics of interconnects than models incorporating exclusively either the R or C components. We also detail a network reduction technique used to simplify the extracted RC network at user specified accuracies to manageable complexities, especially for large VLSI circuits. The model and circuit reduction algorithms are applied to practical sample circuits. Results of simulations illustrating the reduction in circuit complexity and the degree of modeling accuracy by these methods are also given. © 1991 IEEE
Duke Scholars
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Published In
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
DOI
EISSN
1937-4151
ISSN
0278-0070
Publication Date
January 1, 1991
Volume
10
Issue
2
Start / End Page
145 / 149
Related Subject Headings
- Computer Hardware & Architecture
- 4607 Graphics, augmented reality and games
- 4009 Electronics, sensors and digital hardware
- 1006 Computer Hardware
- 0906 Electrical and Electronic Engineering
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Pong, T. S., & Brooke, M. A. (1991). A Parasitics Extraction and Network Reduction Algorithm for Analog VLSI. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 10(2), 145–149. https://doi.org/10.1109/43.68401
Pong, T. S., and M. A. Brooke. “A Parasitics Extraction and Network Reduction Algorithm for Analog VLSI.” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 10, no. 2 (January 1, 1991): 145–49. https://doi.org/10.1109/43.68401.
Pong TS, Brooke MA. A Parasitics Extraction and Network Reduction Algorithm for Analog VLSI. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 1991 Jan 1;10(2):145–9.
Pong, T. S., and M. A. Brooke. “A Parasitics Extraction and Network Reduction Algorithm for Analog VLSI.” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 10, no. 2, Jan. 1991, pp. 145–49. Scopus, doi:10.1109/43.68401.
Pong TS, Brooke MA. A Parasitics Extraction and Network Reduction Algorithm for Analog VLSI. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 1991 Jan 1;10(2):145–149.
Published In
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
DOI
EISSN
1937-4151
ISSN
0278-0070
Publication Date
January 1, 1991
Volume
10
Issue
2
Start / End Page
145 / 149
Related Subject Headings
- Computer Hardware & Architecture
- 4607 Graphics, augmented reality and games
- 4009 Electronics, sensors and digital hardware
- 1006 Computer Hardware
- 0906 Electrical and Electronic Engineering