Fine-grain access control fcw distributed shared memory

Conference Paper

This paper discusses implementations of fine-grain memory access control, which selectively restricts reads and writes to cache-block-sized memory regions. Fine-grain access control forms the basis of efficient cache-coherent shared memory. This paper focuses on low-cost implementations that require little or no additional hardware. These techniques permit efficient implementation of shared memory on a wide range of parallel systems, thereby providing shared-memory codes with a portability previously limited to message passing. This paper categorizes techniques based on wh~ere access control is enforced and where access conflicts are handled. We incorporated three techniques that require no additional hardware into Blizzard, a system that supports distributed shared memory on the CM-5. The first adds a software lookup before each shared-memory rxference by modifying the program's executable. The second uses the memory's error correcting code (ECC) as cache-block valid bits. The third is a hybrid. The software technique ranged from slightly faster to two times slower than the ECC approach. Blizzard's performance is roughly comparable to a hardware shared-memory machine. These results argue that clusters of workstations or personal computers with networks comparable to the CM-5's will be able to support the same shared-memory interfaces as supercomputers.

Full Text

Duke Authors

Cited Authors

  • Schoinas, I; Falsafi, B; Lebeck, AR; Reinhardt, SK; Larus, JR; Wood, DA

Published Date

  • November 1, 1994

Published In

  • International Conference on Architectural Support for Programming Languages and Operating Systems Asplos

Volume / Issue

  • Part F129531 /

Start / End Page

  • 297 - 306

International Standard Book Number 10 (ISBN-10)

  • 0897916603

Digital Object Identifier (DOI)

  • 10.1145/195473.195575

Citation Source

  • Scopus