Three-dimensional, massively parallel, optically interconnected silicon computational hardware and architectures for high-speed IR scene generation
High frame rate infrared scene generation depends on high performance digital processors that are tightly coupled to infrared emitter arrays. Massively parallel image generation hardware can realize the type of high throughput, high frame rate processing that will characterize the next generation of scene generators. This work outlines projects in massively parallel, high throughput image generation hardware using thin film optoelectronic devices which are integrated directly onto low cost silicon integrated circuits. For basic scene generation, an array of thin film emitters are placed on top of digital single instruction stream, multiple data stream (SIMD) parallel processors to provide high performance focal plane generation in a monolithic system. For more complex scene generation, low cost stacked silicon integrated circuits, using through-silicon wafer optoelectronic channels for three dimensional interconnections, form an extremely dense, high throughput, three dimensional parallel processing system. Thin film InGaAsP devices, which operate at wavelengths to which silicon is transparent, are integrated on top of standard foundry silicon integrated circuits so that stacked processor chips can communicate vertically. High speed analog interface circuitry on the Si integrated circuits provides a high bandwidth link between the devices and the digital processing circuitry. This processing approach provides tremendous generality for high frame rate image generation applications in a compact system. Issues addressed include system interfacing, power management, manufacturing tolerances, testing and repair, and system cost and effectiveness.
Cat, HH; Wills, DS; Jokerst, NM; Brooke, MA; Brown, AS
Proceedings of SPIE - The International Society for Optical Engineering
Volume / Issue
Start / End Page