Applying architectural vulnerability analysis to hard faults in the microprocessor
Publication
, Journal Article
Bower, FA; Hower, D; Yilmaz, M; Sorin, DJ; Ozev, S
Published in: Performance Evaluation Review
June 1, 2006
In this paper, we present a new metric, Hard-Fault Architectural Vulnerability Factor (H-AVF), to allow designers to more effectively compare alternate hard-fault tolerance schemes. In order to provide intuition on the use of H-AVF as a metric, we evaluate fault-tolerant level-1 data cache and register file implementations using error correcting codes and a fault-tolerant adder using triple-modular redundancy (TMR). For each of the designs, we compute its H-AVF. We then use these H-AVF values in conjunction with other properties of the design, such as die area and power consumption, to provide composite metrics. The derived metrics provide simple, quantitative measures of the cost-effectiveness of the evaluated designs.
Duke Scholars
Published In
Performance Evaluation Review
DOI
EISSN
0163-5999
ISSN
0163-5999
Publication Date
June 1, 2006
Volume
34
Issue
1
Start / End Page
375 / 376
Related Subject Headings
- Networking & Telecommunications
Citation
APA
Chicago
ICMJE
MLA
NLM
Bower, F. A., Hower, D., Yilmaz, M., Sorin, D. J., & Ozev, S. (2006). Applying architectural vulnerability analysis to hard faults in the microprocessor. Performance Evaluation Review, 34(1), 375–376. https://doi.org/10.1145/1140103.1140327
Bower, F. A., D. Hower, M. Yilmaz, D. J. Sorin, and S. Ozev. “Applying architectural vulnerability analysis to hard faults in the microprocessor.” Performance Evaluation Review 34, no. 1 (June 1, 2006): 375–76. https://doi.org/10.1145/1140103.1140327.
Bower FA, Hower D, Yilmaz M, Sorin DJ, Ozev S. Applying architectural vulnerability analysis to hard faults in the microprocessor. Performance Evaluation Review. 2006 Jun 1;34(1):375–6.
Bower, F. A., et al. “Applying architectural vulnerability analysis to hard faults in the microprocessor.” Performance Evaluation Review, vol. 34, no. 1, June 2006, pp. 375–76. Scopus, doi:10.1145/1140103.1140327.
Bower FA, Hower D, Yilmaz M, Sorin DJ, Ozev S. Applying architectural vulnerability analysis to hard faults in the microprocessor. Performance Evaluation Review. 2006 Jun 1;34(1):375–376.
Published In
Performance Evaluation Review
DOI
EISSN
0163-5999
ISSN
0163-5999
Publication Date
June 1, 2006
Volume
34
Issue
1
Start / End Page
375 / 376
Related Subject Headings
- Networking & Telecommunications