Applying architectural vulnerability analysis to hard faults in the microprocessor
Journal Article
In this paper, we present a new metric, Hard-Fault Architectural Vulnerability Factor (H-AVF), to allow designers to more effectively compare alternate hard-fault tolerance schemes. In order to provide intuition on the use of H-AVF as a metric, we evaluate fault-tolerant level-1 data cache and register file implementations using error correcting codes and a fault-tolerant adder using triple-modular redundancy (TMR). For each of the designs, we compute its H-AVF. We then use these H-AVF values in conjunction with other properties of the design, such as die area and power consumption, to provide composite metrics. The derived metrics provide simple, quantitative measures of the cost-effectiveness of the evaluated designs.
Full Text
Duke Authors
Cited Authors
- Bower, FA; Hower, D; Yilmaz, M; Sorin, DJ; Ozev, S
Published Date
- June 1, 2006
Published In
Volume / Issue
- 34 / 1
Start / End Page
- 375 - 376
Electronic International Standard Serial Number (EISSN)
- 0163-5999
International Standard Serial Number (ISSN)
- 0163-5999
Digital Object Identifier (DOI)
- 10.1145/1140103.1140327
Citation Source
- Scopus