Thermal-aware test access mechanism and wrapper design optimization for system-on-chips

Journal Article (Journal Article)

Rapid advances in semiconductor manufacturing technology have led to higher chip power densities, which places greater emphasis on packaging and temperature control during testing. For system-on-chips, peak power-based scheduling algorithms have been used to optimize tests under specified power constraints. However, imposing power constraints does not always solve the problem of overheating due to the non-uniform distribution of power across the chip. This paper presents a TAM/Wrapper co-design methodology for system-on-chips that ensures thermal safety while still optimizing the test schedule. The method combines a simplified thermal-cost model with a traditional bin-packing algorithm to minimize test time while satisfying temperature constraints. Furthermore, for temperature checking, thermal simulation is done using cycle-accurate power profiles for more realistic results. Experiments show that even a minimal sacrifice in test time can yield a considerable decrease in test temperature as well as the possibility of further lowering temperatures beyond those achieved using traditional power-based test scheduling. Copyright © 2008 The Institute of Electronics, Information and Communication Engineers.

Full Text

Duke Authors

Cited Authors

  • Yu, TE; Yoneda, T; Chakrabarty, K; Fujiwara, H

Published Date

  • January 1, 2008

Published In

Volume / Issue

  • E91-D / 10

Start / End Page

  • 2440 - 2448

Electronic International Standard Serial Number (EISSN)

  • 1745-1361

International Standard Serial Number (ISSN)

  • 0916-8532

Digital Object Identifier (DOI)

  • 10.1093/ietisy/e91-d.10.2440

Citation Source

  • Scopus