High resolution nonlinearity correcting A/D converter architecture
Publication
, Journal Article
Sculley, TL; Brooke, MA
Published in: Proceedings - IEEE International Symposium on Circuits and Systems
January 1, 1993
An architecture is presented for a high resolution analog-to-digital (A/D) converter with tolerance to nonlinearities in the critical timing path as well as offsets and gain errors. An error budget analysis is also included which describes the relationship among the various error source in the converter.
Duke Scholars
Published In
Proceedings - IEEE International Symposium on Circuits and Systems
ISSN
0271-4310
Publication Date
January 1, 1993
Volume
2
Start / End Page
1212 / 1214
Citation
APA
Chicago
ICMJE
MLA
NLM
Sculley, T. L., & Brooke, M. A. (1993). High resolution nonlinearity correcting A/D converter architecture. Proceedings - IEEE International Symposium on Circuits and Systems, 2, 1212–1214.
Sculley, T. L., and M. A. Brooke. “High resolution nonlinearity correcting A/D converter architecture.” Proceedings - IEEE International Symposium on Circuits and Systems 2 (January 1, 1993): 1212–14.
Sculley TL, Brooke MA. High resolution nonlinearity correcting A/D converter architecture. Proceedings - IEEE International Symposium on Circuits and Systems. 1993 Jan 1;2:1212–4.
Sculley, T. L., and M. A. Brooke. “High resolution nonlinearity correcting A/D converter architecture.” Proceedings - IEEE International Symposium on Circuits and Systems, vol. 2, Jan. 1993, pp. 1212–14.
Sculley TL, Brooke MA. High resolution nonlinearity correcting A/D converter architecture. Proceedings - IEEE International Symposium on Circuits and Systems. 1993 Jan 1;2:1212–1214.
Published In
Proceedings - IEEE International Symposium on Circuits and Systems
ISSN
0271-4310
Publication Date
January 1, 1993
Volume
2
Start / End Page
1212 / 1214