A parasitics extraction and network reduction algorithm for VLSI
An algorithm for the extraction of circuit parasitics in integrated circuits using classic transmission line models is discussed. This gives a better account of the DC and AC characteristics of interconnects than models incorporating exclusively either the R or C components. A network reduction technique used to simplify the extracted RC network at user-specified accuracies to manageable complexities, especially for large VLSI circuits, is detailed. The model and circuit reduction algorithms are applied to practical sample circuits. Results of simulations illustrating the reduction in circuit complexity and the degree of modeling accuracy of these methods also given.