Layout-driven test-architecture design and optimization for 3D SoCs under pre-bond test-pin-count constraint


Journal Article

We propose a layout-driven test-architecture design and optimization technique for core-based system-on-chips (SoCs) that are fabricated using three-dimensional (3D) integration. In contrast to prior work, we consider the pre-bond test-pin-count constraint during optimization since these pins occupy large silicon area that cannot be used in functional mode. In addition, the proposed test-architecture design takes the SoC layout into consideration and facilitates the sharing of test wires between pre-bond tests and post-bond test, which significantly reduces the routing cost for a test-access mechanism in 3D technology. Experimental results for the ITC'02 SoC benchmarks circuits demonstrate the effectiveness of the proposed solution. Copyright 2009 ACM.

Full Text

Duke Authors

Cited Authors

  • Jiang, L; Xu, Q; Chakrabarty, K; Mak, TM

Published Date

  • January 1, 2009

Published In

Start / End Page

  • 191 - 196

International Standard Serial Number (ISSN)

  • 1092-3152

Digital Object Identifier (DOI)

  • 10.1145/1687399.1687434

Citation Source

  • Scopus