Efficient test access mechanism optimization for system-on-chip

Published

Journal Article

Test access mechanisms (TAMs) are an important component of a system-on-chip (SOC) test architecture. TAM optimization is necessary to minimize the SOC testing time. We present a fast, heuristic technique for TAM optimization and demonstrate its scalability for several industrial SOCs. Since the TAM optimization problem is NP-hard, recently proposed methods based on integer linear programming and exhaustive enumeration can be used to design limited test architectures with only a very small number of TAMs in a reasonable amount of time. In this paper, we explore a larger solution-space to design efficient test architectures with more TAMs. We show that the SOC testing times obtained using the new heuristic algorithm are comparable to or lower than the testing times obtained using enumeration. Moreover, significant reduction can be obtained in the CPU time compared to enumeration.

Full Text

Duke Authors

Cited Authors

  • Iyengar, V; Chakrabarty, K; Marinissen, EJ

Published Date

  • May 1, 2003

Published In

Volume / Issue

  • 22 / 5

Start / End Page

  • 635 - 643

International Standard Serial Number (ISSN)

  • 0278-0070

Digital Object Identifier (DOI)

  • 10.1109/TCAD.2003.810737

Citation Source

  • Scopus