System-on-a-chip test scheduling with precedence relationships, preemption, and power constraints

Published

Journal Article

Test scheduling is an important problem in system-on-a-chip (SOC) test automation. Efficient test schedules minimize the overall system test application time, avoid test resource conflicts, and limit power dissipation during test mode. In this paper, we present an integrated approach to several test scheduling problems. We first present a method to determine optimal schedules for reasonably sized SOCs with precedence relationships, i.e., schedules that preserve desirable orderings among tests. We also present an efficient heuristic algorithm to schedule tests for large SOCs with precedence constraints in polynomial time. We describe a novel algorithm that uses preemption of tests to obtain efficient schedules for SOCs. Experimental results for an academic SOC and an industrial SOC show that efficient test schedules can be obtained in reasonable CPU time.

Full Text

Duke Authors

Cited Authors

  • Iyengar, V; Chakrabarty, K

Published Date

  • September 1, 2002

Published In

Volume / Issue

  • 21 / 9

Start / End Page

  • 1088 - 1094

International Standard Serial Number (ISSN)

  • 0278-0070

Digital Object Identifier (DOI)

  • 10.1109/TCAD.2002.801102

Citation Source

  • Scopus