Design of built-in test generator circuits using width compression


Journal Article

We present a method for designing test generator circuits (TGC's) that incorporate a precomputed test set TD in the patterns they produce. Our method uses width compression based on the property of d-compatibles as well as compatibles and inverse compatibles and does not require access to a gate-level model of the circuit under test. The TGC consists of a counter, which generates a set of encoded test patterns TE, and a decompression circuit, which consists of simple binary decoders that generate a final sequence containing TD. We show that partially specified test sets, i.e., those that contain a large number of don't-cares, lead to more efficient TGC's. These TGC's are applicable to embedded-core circuits whose detailed designs are not available. We demonstrate the effectiveness of our approach by presenting experimental results on width compression for the ISCAS'85 benchmark circuits and the full-scan versions of the ISCAS'89 benchmark circuits. Index Terms - BIST pattern generation, built-in self-test (BIST), decompression circuit, deterministic BIST, embedded core testing, encoding methods, partially specified test sets, sequence generator. © 1998 IEEE.

Full Text

Duke Authors

Cited Authors

  • Chakrabarty, K; Murray, BT

Published Date

  • December 1, 1998

Published In

Volume / Issue

  • 17 / 10

Start / End Page

  • 1044 - 1051

International Standard Serial Number (ISSN)

  • 0278-0070

Digital Object Identifier (DOI)

  • 10.1109/43.728923

Citation Source

  • Scopus