MODELING RAPID THERMAL ANNEALING PROCESSES FOR SHALLOW JUNCTION FORMATION IN SILICON.
Publication
, Journal Article
Fair, RB; Wortman, JJ; Liu, J
Published in: Technical Digest - International Electron Devices Meeting
January 1, 1983
Duke Scholars
Published In
Technical Digest - International Electron Devices Meeting
DOI
ISSN
0163-1918
Publication Date
January 1, 1983
Start / End Page
658 / 661
Citation
APA
Chicago
ICMJE
MLA
NLM
Fair, R. B., Wortman, J. J., & Liu, J. (1983). MODELING RAPID THERMAL ANNEALING PROCESSES FOR SHALLOW JUNCTION FORMATION IN SILICON. Technical Digest - International Electron Devices Meeting, 658–661. https://doi.org/10.1109/iedm.1983.190593
Fair, R. B., J. J. Wortman, and J. Liu. “MODELING RAPID THERMAL ANNEALING PROCESSES FOR SHALLOW JUNCTION FORMATION IN SILICON.” Technical Digest - International Electron Devices Meeting, January 1, 1983, 658–61. https://doi.org/10.1109/iedm.1983.190593.
Fair RB, Wortman JJ, Liu J. MODELING RAPID THERMAL ANNEALING PROCESSES FOR SHALLOW JUNCTION FORMATION IN SILICON. Technical Digest - International Electron Devices Meeting. 1983 Jan 1;658–61.
Fair, R. B., et al. “MODELING RAPID THERMAL ANNEALING PROCESSES FOR SHALLOW JUNCTION FORMATION IN SILICON.” Technical Digest - International Electron Devices Meeting, Jan. 1983, pp. 658–61. Scopus, doi:10.1109/iedm.1983.190593.
Fair RB, Wortman JJ, Liu J. MODELING RAPID THERMAL ANNEALING PROCESSES FOR SHALLOW JUNCTION FORMATION IN SILICON. Technical Digest - International Electron Devices Meeting. 1983 Jan 1;658–661.
Published In
Technical Digest - International Electron Devices Meeting
DOI
ISSN
0163-1918
Publication Date
January 1, 1983
Start / End Page
658 / 661