The design and verification of a VLSI chip for electrocardiogram data compression

Journal Article

A VLSI architecture for performing electrocardiogram (ECG) data compression is presented. The goals of the chip are to improve both the speed and the density as compared to an off-the-shelf implementation. The complex control sections of the chip were synthesized from a functional description into standard cells, while critical-path arithmetic sections were custom designed. This mix of full custom and standard cell design allows for a trade-off between design time and area, with no penalty in speed performance. The resulting silicon chip, implemented in 1.1 μm CMOS technology, is useful for ECG data collection, compression, and analysis.

Duke Authors

Cited Authors

  • Roy, SC; Krakow, WT; Sacks, B; Batchelor, WE; Bohs, LN; Barr, RC

Published Date

  • December 1, 1990

Start / End Page

  • 170 - 177

Citation Source

  • Scopus