Two novel cache architectures called Pollution Control Caching (PCC) and PCC plus Victim Buffering are presented. Trace driven simulation is used to obtain miss ratio statistics, and analytical models of the expected clock cycles per instruction (E[CPI]) are developed for each architecture and cache size studied. The analytical models are parameterized with the results of the trace driven simulation. The models incorporate provisions to study the effect that on-chip cache size has on access time, and the effect that this and different main memory latencies have on the E[CPI]. Chip area models are also developed for each architecture and used as a basis for comparison. Finally, ANOVA techniques are used to better quantify the differences in the miss rate performance of the cache sizes and cache architectures studied.