A compact CPU architecture for sensor signal processing

Journal Article

This paper proposes a compact, one-bit serial processing CPU architecture for general purpose computing as well as for digital signal processing. The primary design goal is to achieve optimal silicon area, which is one of the critical demands in the area-constrained sensor design with delta sigma signal processing techniques. Based on the coordinate rotation digital computer (CORDIC) algorithm, a general purpose CPU is expanded to implement basic logical functions and arithmatic functions such as linear, trigonometric, and hyperbolic algorithms. Two off-chip memory chips provide single digit serial input and output for data and instructions. © 2006 IEEE.

Duke Authors

Cited Authors

  • Xin, C; Brooke, M

Published Date

  • December 1, 2006

Published In

Start / End Page

  • 45 - 48

International Standard Serial Number (ISSN)

  • 0271-4310

Citation Source

  • Scopus