A 1.4 G samples/sec comb filter design for decimation of sigma-delta modulator output
A new architecture of high-speed comb filter is proposed and simulated. The proposed architecture takes advantage of the concept of carry-save adder and binary signed-digit to minimizes the carry propagation. It has a highly modular architecture and can be used for any order and any word length of comb filter. Also the concept can be applied to the optimization of a general high-speed adder or accumulator. The simulation of the proposed filter can process 1.4 G samples/sec when it is designed using a 0.18 um standard CMOS process. The chip area is 360 um by 140 um. The same architecture can run at 120 M samples/sec using a 1.5 um CMOS process and takes 3360 um by 1630 um in chip area. Discussion and suggestion related to the common comb filter algorithm is also presented.