IRIS: An integrated, scalable focal plane architecture

Journal Article

Wearable video processing systems integrate low cost silicon detectors and analog interface circuitry with massively parallel digital processing on a single chip. While this `imaging system on a chip' can enable many significant new systems, many architectural and technological challenges must be addressed. This paper presents the IRIS architecture in which a detector, analog interface circuitry, and massively parallel digital processing is integrated into a cell that can be tiled into a monolithic array. This pixel level integration offers significant performance, efficiency, and cost advantages over multi-chip and non-interleaved approaches. The IRIS architecture and an example system is described.

Duke Authors

Cited Authors

  • Robinson, WH; Wills, DS; Brooke, M; Jokerst, N

Published Date

  • December 1, 1998

Published In

Volume / Issue

  • 2 /

Start / End Page

  • 184 - 185

International Standard Serial Number (ISSN)

  • 1092-8081

Citation Source

  • Scopus