High density interconnect (HDI) electrical interconnections and vertical optoelectronic (OE) through-Si links for 3D computational systems have been modeled, and compared and contrasted in the areas of latency, size, and power dissipation. Based upon the Semiconductor Industry Association (SIA) Roadmap projections, which indicate interconnection as a challenge area for coming generations of electronics, optoelectronics may serve a role in chip to chip interconnections for massively parallel computational systems.