High speed, smart focal plane processing using integrated photodetectors and Si CMOS VLSI sigma delta analog to digital converters

Journal Article

A high frame rate smart pixel imaging system using an analog to digital converter per pixel in an 8×8 integrated detector array is discussed. The smart pixel architecture enables frame rates of up to 100 kfps operating in a continuous imaging mode. This integrated imaging system is implemented in a digital Si CMOS VLSI, and, to realize scalability, is integrated with an emitter driver circuit for through-Si vertical optical communication down to a second layer of dedicated Si image processing circuitry.

Duke Authors

Cited Authors

  • Joo, Y; Fike, S; Thomas, M; Chung, KS; Brooke, M; Jokerst, NM; Wills, DS

Published Date

  • 1998

Published In

  • LEOS Summer Topical Meeting

Start / End Page

  • 55 - 56