Design issues for through-wafer optoelectronic multicomputer interconnects

Journal Article

This paper presents several design issues associated with the implementation of a three dimensional optically interconnected parallel processing system. A technique for improving bit error rate in low power multistage networks is presented. Error detection codes are transmitted along with message data to guarantee the integrity of the data during each optical hop. To realize three dimensional through-silicon wafer interconnect, thin film emitters and detectors operating at a wavelength of 1.3 μm (to which silicon is transparent) will be bonded to the silicon circuitry. A transfer diaphragm process is used to realize this integration; this process has been used to demonstrate the basic concept: a single silicon circuit has been integrated with both a thin film emitter and detector operating at 1.3 μm wavelength. In this paper, we will utilize one possible integration scenario to illustrate the trade-offs associated with a system of this type, which includes device design, circuit design, and issues which include manufacturability, alignment tolerance, crosstalk, and power dissipation.

Duke Authors

Cited Authors

  • May, P; Wilkinson, ST; Jokerst, NM; Wills, DS; Lee, M; Vendier, O; Bond, SW; Hou, Z; Dagnall, G; Brooke, MA; Brown, A

Published Date

  • December 1, 1995

Published In

  • International Conference on Massively Parallel Processing Using Optical Interconnections (Mppoi), Proceedings

Start / End Page

  • 8 - 15

Citation Source

  • Scopus