Test schedule optimization for multicore SoCs: Handling dynamic voltage scaling and multiple voltage islands

Published

Journal Article

In order to provide high performance with low power consumption, many multicore chips employ dynamic voltage scaling and voltage islands that operate at multiple power-supply voltage levels. Effective defect screening for such chips requires test applications at different operating voltages, which leads to higher test time and test cost compared to systems-on-a-chip (SoCs), which operate at only a single voltage level. We propose test scheduling techniques to minimize the testing time for multicore chips when each core is tested at multiple voltage levels and when it is tested for state retention when the core switches between two voltage levels. The proposed techniques include exact optimization based on integer linear programming and fast heuristic methods. Experimental results for two test-case SoCs from the industry highlight the effectiveness of the proposed method. © 1982-2012 IEEE.

Full Text

Duke Authors

Cited Authors

  • Kavousianos, X; Chakrabarty, K; Jain, A; Parekhji, R

Published Date

  • October 29, 2012

Published In

Volume / Issue

  • 31 / 11

Start / End Page

  • 1754 - 1766

International Standard Serial Number (ISSN)

  • 0278-0070

Digital Object Identifier (DOI)

  • 10.1109/TCAD.2012.2203600

Citation Source

  • Scopus