TSV defects and TSV-induced circuit failures: The third dimension in test and design-for-test

Journal Article

3D integrated circuits (3D ICs) based on through-silicon vias (TSVs) have emerged as a promising solution for overcoming interconnect and power bottlenecks in IC design. However, testing of 3D ICs remains a significant challenge, and breakthroughs in test technology are needed to make 3D integration commercially viable. This paper first presents an overview of TSV-related defects and the impact of TSVs in the form of new defects in devices and interconnects. The paper next describes recent advances in testing, diagnosis, and design-for-testability for 3D ICs and techniques for defect tolerance using redundancy and repair. Topics covered include various types of TSV defects, stress-induced mobility and threshold-voltage variation in devices, stress-induced electromigration in inter-connects, pre-bond and test-bond testing (including TSV probing), and optimization techniques for defect tolerance. © 2012 IEEE.

Full Text

Duke Authors

Cited Authors

  • Chakrabarty, K; Deutsch, S; Thapliyal, H; Ye, F

Published Date

  • September 28, 2012

Published In

International Standard Serial Number (ISSN)

  • 1541-7026

Digital Object Identifier (DOI)

  • 10.1109/IRPS.2012.6241859

Citation Source

  • Scopus