Rapid generation of thermal-safe test schedules

Journal Article

Overheating has been acknowledged as a major issue in testing complex SOCs. Several power constrained system-level DFT solutions (power constrained test scheduling) have recently been proposed to tackle this problem. However, as it will be shown in this paper, imposing a chip-level maximum power constraint doesn't necessarily avoid local overheating due to the non-uniform distribution of power across the chip. This paper proposes a new approach for dealing with overheating during test, by embedding thermal awareness into test scheduling. The proposed approach facilitates rapid generation of thermal-safer test schedules without requiring time-consuming thermal simulations. This is achieved by employing a lowcomplexity test session thermal model used to guide the test schedule generation algorithm. This approach reduces the chances of a design re-spin due to potential overheating during test.

Full Text

Duke Authors

Cited Authors

  • Rosinger, P; Al-Hashimi, B; Chakrabarty, K

Published Date

  • December 1, 2005

Published In

Volume / Issue

  • II /

Start / End Page

  • 840 - 845

International Standard Serial Number (ISSN)

  • 1530-1591

Digital Object Identifier (DOI)

  • 10.1109/DATE.2005.252

Citation Source

  • Scopus