Identification of error-capturing scan cells in scan-BIST with applications to system-on-chip

Published

Journal Article

We present a new partition-based fault-diagnosis technique for identifying error-capturing scan cells in a scan-BIST environment. This approach relies on a two-step scan chain partitioning scheme. In the first step, an interval-based partitioning scheme is used to generate a small number of partitions, where each element of a partition consists of a set of consecutive scan cells. In the second step, additional partitions are created using a previously proposed random-selection partitioning method. Two-step partitioning provides higher diagnostic resolution than previous schemes that rely either on random-selection partitioning or deterministic partitioning. We show via experiments that the proposed method requires only a small amount of additional hardware. The proposed scheme is especially suitable for a system-on-chip (SOC) composed of multiple embedded cores, where test access is provided by means of a TestRail that is threaded through the internal scan chains of the embedded cores. We present analytical results to characterize two-step partitioning, and present experimental results for the six largest ISCAS'89 benchmark circuits and two SOCs crafted from some of the ISCAS'89 circuits.

Full Text

Duke Authors

Cited Authors

  • Liu, C; Chakrabarty, K

Published Date

  • October 1, 2004

Published In

Volume / Issue

  • 23 / 10

Start / End Page

  • 1447 - 1459

International Standard Serial Number (ISSN)

  • 0278-0070

Digital Object Identifier (DOI)

  • 10.1109/TCAD.2004.833620

Citation Source

  • Scopus