A deterministic scan-BIST architecture with application to field testing of high-availability systems


Journal Article

We propose an autonomous, deterministic scan-BIST architecture that allows compact, precomputed test sets with complete fault coverage to be used for field testing. The use of such short test sequences is desirable in safety-critical systems since it reduces the error latency. It also reduces testing time and therefore allows periodic field testing to be carried out with low system downtime. We synthesize the BIST logic for several ISCAS 89 benchmarks and industrial circuit modules and show that the BIST overhead is low in all cases. The proposed design can also be efficiently used with a mixed-mode BIST strategy. © 2001 IEEE.

Full Text

Duke Authors

Cited Authors

  • Swaminathan, S; Chakrabarty, K

Published Date

  • January 1, 2001

Published In

Start / End Page

  • 259 - 262

International Standard Serial Number (ISSN)

  • 0886-5930

Digital Object Identifier (DOI)

  • 10.1109/CICC.2001.929768

Citation Source

  • Scopus