Built-in self testing of high-performance circuits using twisted-ring counters

Journal Article (Journal Article)

We present an enhanced built-in self-test (BIST) architecture for high-performance circuits. Test patterns are generated by reseeding a twisted-ring counter. We show that a small number of seeds is adequate for generating test sequences that embed complete test sets for the ISCAS benchmark circuits. The seed patterns can either be stored on-chip or scanned in using a low-cost, slower tester. The seeds can thus be viewed as an encoded version of the test set - during testing, the patterns derived from the seeds are applied test-per-clock to the circuit under test. This allows us to effectively combine high-quality BIST with external testing using slower testers.

Full Text

Duke Authors

Cited Authors

  • Chakrabarty, K; Swaminathan, S

Published Date

  • January 1, 2000

Published In

Volume / Issue

  • 1 /

Start / End Page

  • I-72-I-75 -

International Standard Serial Number (ISSN)

  • 0271-4310

Digital Object Identifier (DOI)

  • 10.1109/ISCAS.2000.857029

Citation Source

  • Scopus