A self-organizing defect tolerant SIMD architecture


Journal Article

The continual decrease in transistor size (through either scaled CMOS or emerging nanotechnologies) promises to usher in an era of tera to peta-scale integration but with increasing defects. Regardless of fabrication methodology (top-down or bottom-up), defect-tolerant architectures are necessary to exploit the full potential of future increased device densities. This article explores a defect-tolerant SIMD architecture (SOSA) that self-organizes a large number of limited capability nodes with high defect rates into SIMD processing elements. Simulation results show that SOSA matches or exceeds the performance of conventional systems for moderate to large problems, but with lower power density. © 2007 ACM.

Full Text

Duke Authors

Cited Authors

  • Patwardhan, J; Dwyer, C; Lebeck, AR

Published Date

  • July 1, 2007

Published In

Volume / Issue

  • 3 / 2

Electronic International Standard Serial Number (EISSN)

  • 1550-4840

International Standard Serial Number (ISSN)

  • 1550-4832

Digital Object Identifier (DOI)

  • 10.1145/1265949.1265956

Citation Source

  • Scopus