Flexible register management using reference counting

Published

Conference Paper

Conventional out-of-order processors that use a unified physical register file allocate and reclaim registers explicitly using a free list that operates as a circular queue. We describe and evaluate a more flexible register management scheme - reference counting. We implement reference counting using a bit-matrix with a column for every physical register and a row for every entity that can hold a physical register, e.g., an in-flight instruction. Columns are NOR'ed together to create a bitvector free list from which registers are allocated using priority encoders. We describe reference counting designs that support micro-architectural techniques including register file power gating, dynamic register move elimination, register file checkpointing, and latency tolerant execution. Performance and circuit simulation show that the energy cost of reference counting is low and is easily recouped by the savings of the techniques it enables. © 2012 IEEE.

Full Text

Duke Authors

Cited Authors

  • Battle, S; Hilton, AD; Hempstead, M; Roth, A

Published Date

  • May 3, 2012

Published In

Start / End Page

  • 273 - 284

International Standard Serial Number (ISSN)

  • 1530-0897

International Standard Book Number 13 (ISBN-13)

  • 9781467308243

Digital Object Identifier (DOI)

  • 10.1109/HPCA.2012.6169033

Citation Source

  • Scopus