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Design and optimization of board-level optical clock distribution network for high-performance optoelectronic system-on-a-packages

Publication ,  Journal Article
Seo, CS; Chatterjee, A; Cho, SY; Jokerst, NM
Published in: Proceedings of the ACM Great Lakes Symposium on VLSI
January 1, 2004

A new approach to optical clock distribution utilizing optical waveguide interconnect technology is introduced. In this paper, we develop a new algorithm for design and optimization of board-level optical clock distribution network for high-performance optoelectronic system-on-a-packages. The optimization approach takes into account bending and propagation losses of optical waveguides. Less than 26.1psec in signal timing skew is obtained for a signal flight time of 614.38psec. About 15% reduction in optical power consumption is also obtained over clock nets routed with existing (optical) methods.

Duke Scholars

Published In

Proceedings of the ACM Great Lakes Symposium on VLSI

DOI

Publication Date

January 1, 2004

Start / End Page

292 / 297
 

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Seo, C. S., Chatterjee, A., Cho, S. Y., & Jokerst, N. M. (2004). Design and optimization of board-level optical clock distribution network for high-performance optoelectronic system-on-a-packages. Proceedings of the ACM Great Lakes Symposium on VLSI, 292–297. https://doi.org/10.1145/988952.989023
Seo, C. S., A. Chatterjee, S. Y. Cho, and N. M. Jokerst. “Design and optimization of board-level optical clock distribution network for high-performance optoelectronic system-on-a-packages.” Proceedings of the ACM Great Lakes Symposium on VLSI, January 1, 2004, 292–97. https://doi.org/10.1145/988952.989023.
Seo CS, Chatterjee A, Cho SY, Jokerst NM. Design and optimization of board-level optical clock distribution network for high-performance optoelectronic system-on-a-packages. Proceedings of the ACM Great Lakes Symposium on VLSI. 2004 Jan 1;292–7.
Seo, C. S., et al. “Design and optimization of board-level optical clock distribution network for high-performance optoelectronic system-on-a-packages.” Proceedings of the ACM Great Lakes Symposium on VLSI, Jan. 2004, pp. 292–97. Scopus, doi:10.1145/988952.989023.
Seo CS, Chatterjee A, Cho SY, Jokerst NM. Design and optimization of board-level optical clock distribution network for high-performance optoelectronic system-on-a-packages. Proceedings of the ACM Great Lakes Symposium on VLSI. 2004 Jan 1;292–297.

Published In

Proceedings of the ACM Great Lakes Symposium on VLSI

DOI

Publication Date

January 1, 2004

Start / End Page

292 / 297