Address translation aware memory consistency


Journal Article

Computer systems with virtual memory are susceptible to design bugs and runtime faults in their address translation systems. Detecting bugs and faults requires a clear specification of correct behavior. A new framework for address translation aware memory consistency models addresses this need. © 2011 IEEE.

Full Text

Duke Authors

Cited Authors

  • Romanescu, B; Lebeck, A; Sorin, DJ

Published Date

  • January 1, 2011

Published In

Volume / Issue

  • 31 / 1

Start / End Page

  • 109 - 118

International Standard Serial Number (ISSN)

  • 0272-1732

Digital Object Identifier (DOI)

  • 10.1109/MM.2010.99

Citation Source

  • Scopus