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A large, fast instruction window for tolerating cache misses

Publication ,  Conference
Lebeck, AR; Koppanalil, J; Li, T; Patwardhan, J; Rotenberg, E
Published in: Conference Proceedings - Annual International Symposium on Computer Architecture, ISCA
January 1, 2002

Instruction window size is an important design parameter for many modern processors. Large instruction windows offer the potential advantage of exposing large amounts of instruction level parallelism. Unfortunately, naively scaling conventional window designs can significantly degrade clock cycle time, undermining the benefits of increased parallelism. This paper presents a new instruction window, design targeted at achieving the latency tolerance of large windows with the clock cycle time of small windows. The key observation is that instructions dependent on a long latency operation (e.g., cache miss) cannot execute until that source operation completes. These instructions are moved out of the conventional, small, issue queue to a much larger waiting instruction buffer (WIB). When the long latency operation completes, the instructions are reinserted into the issue queue. In this paper, we focus specifically on load cache misses and their dependent instructions. Simulations reveal that, for an 8-way processor, a 2 K-entry WIB with a 32-entry issue queue can achieve speedups of 20%, 84%, and 50% over a conventional 32-entry issue queue for a subset of the SPEC CINT2000, SPEC CFP2000, and Olden bench-marks, respectively.

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Published In

Conference Proceedings - Annual International Symposium on Computer Architecture, ISCA

DOI

ISSN

0884-7495

Publication Date

January 1, 2002

Start / End Page

59 / 70
 

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Lebeck, A. R., Koppanalil, J., Li, T., Patwardhan, J., & Rotenberg, E. (2002). A large, fast instruction window for tolerating cache misses. In Conference Proceedings - Annual International Symposium on Computer Architecture, ISCA (pp. 59–70). https://doi.org/10.1109/ISCA.2002.1003562
Lebeck, A. R., J. Koppanalil, T. Li, J. Patwardhan, and E. Rotenberg. “A large, fast instruction window for tolerating cache misses.” In Conference Proceedings - Annual International Symposium on Computer Architecture, ISCA, 59–70, 2002. https://doi.org/10.1109/ISCA.2002.1003562.
Lebeck AR, Koppanalil J, Li T, Patwardhan J, Rotenberg E. A large, fast instruction window for tolerating cache misses. In: Conference Proceedings - Annual International Symposium on Computer Architecture, ISCA. 2002. p. 59–70.
Lebeck, A. R., et al. “A large, fast instruction window for tolerating cache misses.” Conference Proceedings - Annual International Symposium on Computer Architecture, ISCA, 2002, pp. 59–70. Scopus, doi:10.1109/ISCA.2002.1003562.
Lebeck AR, Koppanalil J, Li T, Patwardhan J, Rotenberg E. A large, fast instruction window for tolerating cache misses. Conference Proceedings - Annual International Symposium on Computer Architecture, ISCA. 2002. p. 59–70.

Published In

Conference Proceedings - Annual International Symposium on Computer Architecture, ISCA

DOI

ISSN

0884-7495

Publication Date

January 1, 2002

Start / End Page

59 / 70