Memory controller policies for DRAM power management

Conference Paper

The increasing importance of energy efficiency has produced a multitude of hardware devices with various power management features. This paper investigates memory controller policies for manipulating DRAM power states in cache-based systems. We develop an analytic model that approximates the idle time of DRAM chips using an exponential distribution, and validate our model against trace-driven simulations. Our results show that, for our benchmarks, the simple policy of immediately transitioning a DRAM chip to a lower power state when it becomes idle is superior to more sophisticated policies that try to predict DRAM chip idle time.

Full Text

Duke Authors

Cited Authors

  • Fan, X; Ellis, CS; Lebeck, AR

Published Date

  • January 1, 2001

Published In

  • Proceedings of the International Symposium on Low Power Electronics and Design, Digest of Technical Papers

Start / End Page

  • 129 - 134

Digital Object Identifier (DOI)

  • 10.1145/383082.383118

Citation Source

  • Scopus