Design and test strategies for microarchitectural post-fabrication tuning

Published

Journal Article

Process variations are a major hurdle for continued technology scaling. Both systematic and random variations will affect the critical delay of fabricated chips, causing a wide frequency and power distribution. Tuning techniques adapt the microarchitecture to mitigate the impact of variations at post-fabrication testing time. This paper proposes a new post-fabrication testing framework that accounts for testing costs. This framework uses on-chip canary circuits to capture systematic variation while using statistical analysis to estimate random variation. We derive regression models to predict chip performance and power. These techniques comprise an integrated framework that identifies the most energy efficient post-fabrication tuning configuration for each chip. © 2009 IEEE.

Full Text

Duke Authors

Cited Authors

  • Liang, X; Lee, BC; Wei, GY; Brooks, D

Published Date

  • December 1, 2009

Published In

Start / End Page

  • 84 - 90

International Standard Serial Number (ISSN)

  • 1063-6404

Digital Object Identifier (DOI)

  • 10.1109/ICCD.2009.5413170

Citation Source

  • Scopus