Empirical performance models for 3T1D memories

Journal Article

Process variation poses a threat to the performance and reliability of the 6T SRAM cell. Research has turned to new memory cell designs, such as the 3T1D DRAM cell, as potential replacement designs. If designers are to consider 3T1D memory architectures, performance models are needed to better understand memory cell behavior. We propose a decoupled approach for collecting Monte Carlo HSPICE data, reducing simulation times by simulating memory array components separately based on their contribution to the worst-case critical path. We use this Monte Carlo data to train regression models, which accurately predict retention and access times of a 3T1D memory array with a median error of 7.39%. ©2009 IEEE.

Full Text

Duke Authors

Cited Authors

  • Lovin, K; Lee, BC; Liang, X; Brooks, D; Wei, GY

Published Date

  • December 1, 2009

Published In

Start / End Page

  • 398 - 403

International Standard Serial Number (ISSN)

  • 1063-6404

Digital Object Identifier (DOI)

  • 10.1109/ICCD.2009.5413124

Citation Source

  • Scopus