Efficiency trends and limits from comprehensive microarchitectural adaptivity

Published

Journal Article

Increasing demand for power-efficient, high-performance computing requires tuning applications and/or the underlying hardware to improve the mapping between workload heterogeneity and computational resources. To assess the potential benefits of hardware tuning, we propose a framework that leverages synergistic interactions between recent advances in (a) sampling, (b) predictive modeling, and (c) optimization heuristics. This framework enables qualitatively new capabilities in analyzing the performance and power characteristics of adaptive microarchitectures. For the first time, we are able to simultaneously consider high temporal and comprehensive spatial adaptivity. In particular, we optimize efficiency for many, short adaptive intervals and identify the best configuration of 15 parameters, which define a space of 240B point. With frequent sub-application reconfiguration and a fully reconfigurable hardware substrate, adaptive microarchitectures achieve bips 3 /w efficiency gains of up to 5.3x (median 2.4x) relative to their static counterparts already optimized for a given application. This 5.3x efficiency gain is derived from a 1.6x performance gain and 0.8x power reduction. Although several applications achieve a significant fraction of their potential efficiency with as few as three adaptive parameters, the three most significant parameters differ across applications. These differences motivate a hardware substrate capable of comprehensive adaptivity to meet these diverse application requirements. Copyright © 2008 ACM.

Full Text

Duke Authors

Cited Authors

  • Lee, BC; Brooks, D

Published Date

  • January 1, 2008

Published In

Volume / Issue

  • 42 / 2

Start / End Page

  • 36 - 47

International Standard Serial Number (ISSN)

  • 0163-5980

Digital Object Identifier (DOI)

  • 10.1145/1353535.1346288

Citation Source

  • Scopus