Performance models for evaluation and automatic tuning of symmetric sparse matrix-vector multiply

Published

Journal Article

We present optimizations for sparse matrix-vector multiply SpMV and its generalization to multiple vectors, SpMM, when the matrix is symmetric: (1) symmetric storage, (2) register blocking, and (3) vector blocking. Combined with register blocking, symmetry saves more than 50% in matrix storage. We also show performance speedups of 2.1× for SpMV and 2.6× for SpMM, when compared to the best non-symmetric register blocked implementation. We present an approach for the selection of tuning parameters, based on empirical modeling and search that consists of three steps: (1) Off-line benchmark, (2) Runtime search, and (3) Heuristic performance model. This approach generally selects parameters to achieve performance with 85% of that achieved with exhaustive search. We evaluate our implementations with respect to upper bounds on performance. Our model bounds performance by considering only the cost of memory operations and using lower bounds on the number of cache misses. Our optimized codes are within 68% of the upper bounds.

Duke Authors

Cited Authors

  • Lee Benjamin, BC; Vuduc, RW; Demmel, JW; Yelick, KA

Published Date

  • December 17, 2004

Published In

Start / End Page

  • 169 - 176

International Standard Serial Number (ISSN)

  • 0190-3918

Citation Source

  • Scopus