Empirical evaluation of randomly-wired multistage networks
Publication
, Journal Article
Leighton, T; Lisinski, D; Maggs, B
Published in: Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
September 1, 1990
Experimental data are presented indicating that multistage interconnection networks with randomly positioned wires are likely to be substantially better for message routing applications than traditional multistage networks, such as the butterfly. The data are presented for a variety of routing models, including store-and-forward routing, cut-through routing, and circuit switching, as well as for scenarios in which a potentially large number of switches are faulty. In most cases, the differences are dramatic, particularly when several switches in the network are faulty. The data provide empirical confirmation of recent theoretical work.
Duke Scholars
Published In
Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
Publication Date
September 1, 1990
Start / End Page
380 / 385
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Leighton, T., Lisinski, D., & Maggs, B. (1990). Empirical evaluation of randomly-wired multistage networks. Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors, 380–385.
Leighton, T., D. Lisinski, and B. Maggs. “Empirical evaluation of randomly-wired multistage networks.” Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors, September 1, 1990, 380–85.
Leighton T, Lisinski D, Maggs B. Empirical evaluation of randomly-wired multistage networks. Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors. 1990 Sep 1;380–5.
Leighton, T., et al. “Empirical evaluation of randomly-wired multistage networks.” Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors, Sept. 1990, pp. 380–85.
Leighton T, Lisinski D, Maggs B. Empirical evaluation of randomly-wired multistage networks. Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors. 1990 Sep 1;380–385.
Published In
Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
Publication Date
September 1, 1990
Start / End Page
380 / 385