This paper discusses the simulation needs of deep-submicron MOSFETs beyond the 100 nm technology generation where the tunneling of carriers through the gate dielectric will become a vital issue in device design, optimization, and characterization. We present simulation results of Tunnel-PISCES, a MOSFET device simulator where tunneling in the gate dielectric is implemented in a self-consistent manner with the device equations in the substrate. Simulation results of trends in the gate, substrate, and drain currents with oxide scaling are presented. The drain-current turnaround effect is explained by considering the role of the voltage drop across the polysilicon gate resistance in determining the device gate tunneling conditions. © 1999 Materials Research Society.