On the Design and Implementation of a Lossless Data Compression and Decompression Chip

Published

Journal Article

A lossless data compression and decompression (LDCD) algorithm based on the notion of textual substitution has been implemented in silicon using a linear systolic array architecture. This algorithm employs a model where the encoder and decoder each have a finite amount of memory which is referred to as the dictionary. Compression is achieved by finding matches between the dictionary and the input data stream whereby a substitution is made in the data stream by an index referencing the corresponding dictionary entry. The LDCD system is built using 30 application-specific integrated circuits (ASIC’s) each containing 126 identical processing elements (PE’s) which perform both the encoding and decoding function at clock rates up to 20 MHz. © 1993 IEEE

Full Text

Duke Authors

Cited Authors

  • Storer, JA; Markas, T; Royals, M; Kanopoulos, N; Reif, JH

Published Date

  • January 1, 1993

Published In

Volume / Issue

  • 28 / 9

Start / End Page

  • 948 - 953

Electronic International Standard Serial Number (EISSN)

  • 1558-173X

International Standard Serial Number (ISSN)

  • 0018-9200

Digital Object Identifier (DOI)

  • 10.1109/4.236174

Citation Source

  • Scopus