Efficient VLSI fault simulation

Published

Journal Article

Let C be an acyclic Boolean circuit with n gates and ≤ n inputs. A circuit manufacture error may result in a "Stuck-at" (S-A) fault in a circuit identical to C except a gate v only outputs a fixed Boolean value. The S-A fault simulation problem for C is to determine all possible (S-A) faults which can be detected (i.e., faults circuit and C would give distinct outputs) by a given test pattern input. We consider the case where C is a tree (i.e., has fan-out 1.). We give a practical algorithm for fault simulation which simultaneously determines all detectable S-A faults for every gate in the circuit tree C. Our algorithm required only the evaluation of a circuit FS(C) which has ≤ 7n gates and has depth ≤ 3(d + 1), when d is the depth of C. Thus the sequential time of our algorithm is ≤ 7n, and the parallel time is ≤ 3(d + 1). Furthermore, FS(C) requires only a small constant factor more VLSI area than does the original circuit C. We also extend our results to get efficient methods for fault simulation of oblivious VLSI circuits with feedback lines. © 1992.

Full Text

Duke Authors

Cited Authors

  • Reif, JH

Published Date

  • January 1, 1993

Published In

Volume / Issue

  • 25 / 2

Start / End Page

  • 15 - 32

International Standard Serial Number (ISSN)

  • 0898-1221

Digital Object Identifier (DOI)

  • 10.1016/0898-1221(93)90219-L

Citation Source

  • Scopus