BLITZEN: A highly integrated massively parallel machine
The goal of the BLITZEN project is to construct a physically small, massively parallel, high-performance machine. This paper presents the architecture, organization, and feature set of a highly integrated SIMD array processing chip which has been custom designed and fabricated for this purpose at the Microelectronics Center of North Carolina. The chip has 128 processing elements (PEs), each with 1K bits of static RAM. Unique local control features include the ability to modify the global memory address with data local to each PE, and complementary operations based on a condition register. With a 16K PE system (only 128 custom chips are needed for this), operating at 20 MHz, data I/O can take place at 10,240 megabytes per second through a new method using a 4-bit bus for each set of 16 PEs. A 16K PE system can perform IEEE standard 32-bit floating-point multiplication at a rate greater than 450 megaflops. Fixed-point addition on 32-bit data exceeds the rate of three billion operations per second. Since the processors are bit-serial devices, performance rates improve with shorter word lengths. The BLITZEN chip is one of the first to incorporate over 1.1 million transistors on a single die. It was designed with 1.25-pm, two-level metal, CMOS design rules on an 11.0 by 11.7-mm die. © 1990.
Blevins, DW; Dams, EW; Heaton, RA; Reif, JH
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